In the past, one typical technique for forming chip carriers having multiple voltage planes, i.e., at least two voltage planes, and multiple signal planes, i.e., at least two signal planes (2s/2p) using organic dielectric material has relied on mechanically drilling holes in the voltage planes and particularly mechanically drilling holes in the voltage planes after they have been laminated to a substrate such as FR4 material, which is a glass reinforced epoxy resin. This drilling has several drawbacks. First, drilling is extremely costly in that individual holes must be drilled successively and precisely on a grid. Second, the minimum hole diameter is limited, typically the minimum being from 0.006 inches to 0.008 inches, which results in a minimum land diameter of 0.010 to 0.014 inches, particularly in subtractive processing. Moreover, drilling can lead to reliability problems caused by cathodic and anodic filament plating growth along the glass fibers, which may be damaged by the drilling, and this causes either failure or out of specification parts. Additionally, power distribution in a typically drilled organic chip carrier is poor due to the large amount of copper that must be etched away to provide clearance or tolerance for the plated through holes due to the relatively large grid size required.
All of these factors result in a minimum I/O grid of 0.018 inches to 0.02 inches. As the technology advances, a desirable I/O grid is of 0.010 inches to accommodate flip chip attachment (i.e., solder ball or C4 joints).